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IRL5602S
Peak Diode Recovery dv/dt Test Circuit
D.U.T *
+
?
Circuit Layout Considerations
· Low Stray Inductance
· Ground Plane
· Low Leakage Inductance
Current Transformer
-
+
?
-
-
?
+
?
V GS
R G
· dv/dt controlled by R G
· I SD controlled by Duty Factor "D"
· D.U.T. - Device Under Test
+
-
V DD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[ V GS =10V ] ***
D.U.T. I SD Waveform
Reverse
Recovery
Body Diode Forward
Current
Current
di/dt
D.U.T. V DS Waveform
Diode Recovery
Re-Applied
dv/dt
[ V DD ]
Voltage
Inductor Curent
Body Diode
Ripple  ≤  5%
Forward Drop
[ I SD ]
*** V GS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
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